Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch have achieved high memory cell densities. One of the simplest circuits for providing a small dynamic memory cell is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each cell employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line.
In also commonly assigned U.S. Pat. Nos. 3,811,076 by W. M. Smith, and 3,841,926 by R. R. Garnache and W. M. Smith, both filed on Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the hereinabove identified Dennard patent which utilizes a layer of doped polysilicon and an N+ diffusion region in a P type conductivity semiconductor substrate separated by a dielectric medium disposed on the surface of the semiconductor substrate for forming the storage capacitor of the cell. The polysilicon layer extends beyond the storage capacitor to act as a field shield between adjacent cells by applying a negative bias or fixed negative potential to the polysilicon layer. The N+ diffusion region of the storage capacitor is formed by using a doped segment of an insulating layer disposed on the surface of the semiconductor substrate and outdiffusing the dopant into the substrate.
Although the cells described hereinabove do provide memories having a high density of cells in a planar or two dimensional arrangement, yet each cell does require a significant given area of semiconductor substrate surface. To reduce the size of the given surface area for each cell, structures have been made wherein a semiconductor device or a cell is formed in a three dimensional arrangement. In commonly assigned U.S. Pat. No. 4,295,924, filed on Dec. 17, 1979 by R. R. Garnache and D. M. Kenney, there is disclosed a semiconductor device located within a groove or trench with a self-aligned conductive layer formed on a wall of the trench either directly or on a supporting insulating layer as an element of the device. A memory cell formed in a groove or trench is described in commonly assigned U.S. Pat. No. 4,335,450, filed on Jan. 30, 1980, by D. R. Thomas, wherein there is disclosed a cell having a transistor disposed on a sidewall of a groove or trench with the storage node disposed below the transistor. Also U.S. Pat. No. 4,327,476, filed on Nov. 28, 1980, describes a vertical cell having the storage capacitor in a well or trench.
Furthermore, commonly assigned U.S. Pat. No. 4,462,040, filed on Mar. 30, 1980, by I. T. Ho and J. Riseman, discloses a one device dynamic random access memory utilizing a trench having vertical sidewalls with the storage capacitor and the transfer device located within the trench, and U.S. Pat. Nos. 4,271,418, filed on Oct. 29, 1979, and 4,225,945, filed on June 6, 1977, and commonly assigned U.S. patent application having Ser. No. 793,401, filed on Oct. 31, 1985, by D. M. Kenney, now U.S. Pat. No. 4,785,337, and IBM Technical Disclosure Bulletin, Vol. 27, No. 2, July 1984, pp. 1313 to 1320, by C. G. Jambotkar, teach a one device memory cell formed in a groove or trench with the storage node located at the bottom of the trench, the bit/sense line at the top of this structure and the transfer device on the sidewall of the trench.
Commonly assigned U.S. patent application having Ser. No. 858,787, filed on May 2, 1986, by B. F. Fitzgerald, K. Y. Nguyen and S. V. Nguyen, now U.S. Pat. No. 4,811,067, describes a dynamic memory cell wherein the switching device is located at the bottom of the trench, with the storage capacitor and the bit/sense line being formed along opposite sidewalls of the trench.
U.S. Pat. No. 4,673,962, filed Mar. 21, 1985, discloses a memory structure wherein a pair of cells are formed on a semiconductor substrate, each cell having a polysilicon storage node located on a sidewall of a trench opposite that of the other cell.
Commonly assigned U.S. Pat. No. 4,769,786, filed on July 15, 1986, by R. R, Garnache and D. M. Kenney, discloses a memory circuit wherein each of the memory cells requires only two lithographic squares of the surface of a semiconductor substrate, wherein one lithographic square is defined by the intersection of two orthogonally arranged lithographic lines, each line being of a given width, e.g., less than a micron, as used in forming elements of devices in integrated semiconductor circuits. In the memory circuit of this patent, two memory cells are formed at the intersection of a trench and a bit/sense line. In the hereinabove cited prior art, none of the references except for the commonly assigned U.S. Pat. No. 4,769,786 and the U.S. Pat. No. 4,673,962 disclose a very small memory cell which utilizes a semiconductor substrate surface area of less than four lithographic squares.